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STA500
30V 3.5A QUAD POWER HALF BRIDGE
s
MINIMUM INPUT OUTPUT PULSE WIDTH DISTORTION 200m RdsON COMPLEMENTARY DMOS OUTPUT STAGE CMOS COMPATIBLE LOGIC INPUTS THERMAL PROTECTION THERMAL WARNING OUTPUT OVERVOLTAGE, UNDERVOLTAGE PROTECTION
MULTIPOWER BCD TECHNOLOGY
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s s s s
PowerSO36 ORDERING NUMBER: STA500
current capability. DESCRIPTION STA500 is a monolithic quad half bridge stage in Multipower BCD Technology. The device can be used as dual bridge or reconfigured, by connecting CONFIG pin to Vdd pin, as single bridge with double current capability, and as half bridge (Binary mode) with half AUDIO APPLICATION CIRCUIT (Dual BTL)
VCC1A IN1A IN1A +3.3V IBIAS CONFIG PWRDN R57 10K R59 10K C58 100nF TH_WAR IN1B VDD VDD VSS VSS C58 100nF C53 100nF C60 100nF IN2A VCCSIGN VCCSIGN IN2A GND-Reg GND-Clean 21 22 33 34 M17 35 8 9 36 31 20 19 M16 M15 REGULATORS 7 VCC2A C32 1F OUT2A OUT2A 6 GND2A PWRDN FAULT 23 24 25 27 26 TRI-STATE PROTECTIONS & LOGIC M5 28 30 M4 13 M2 29 M3 15 17 16 C30 1F OUT1A OUT1A 14 GND1A C52 330pF +VCC C55 1000F
The device is particulary designed to make the output stage of a stereo All-Digital High Efficiency (DDXTM) amplifier capable to deliver 30 + 30W output power on 8 load and 60W on 8 load in bridge BTL configuration or mono 60W on 4 load. The input pins have threshold proportional to Ibias pin voltage.
L18 22H C20 100nF R98 6 C99 100nF C23 470nF C101 100nF
12
VCC1B C31 1F OUT1B OUT1B GND1B R63 20 R100 6 C21 100nF L19 22H
11 10
TH_WAR IN1B
L113 22H C110 100nF C109 330pF R103 6 R104 20 C107 100nF C108 470nF C106 100nF
4
VCC2B C33 1F OUT2B OUT2B
R102 6 C111 100nF
3 2
IN2B
IN2B GNDSUB
32 M14
L112 22H
1
5
GND2B
D00AU1148B
July 2003
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PIN FUNCTION
N 1 35 ; 36 15 12 7 4 14 13 6 5 16 ; 17 10 ; 11 8;9 2;3 29 30 31 32 21 ; 22 33 ; 34 25 26 27 24 28 19 23 18 20 Pin GND-SUB Vcc Sign Vcc1A Vcc1B Vcc2A Vcc2B GND1A GND1B GND2A GND2B OUT1A OUT1B OUT2A OUT2B IN1A IN1B IN2A IN2B Vdd Vss PWRDN TRI-STATE FAULT CONFIG TH-WAR GND-clean IBIAS NC GND-Reg Substrate ground Signal Positive supply Positive Supply Positive Supply Positive Supply Positive Supply Negative Supply Negative Supply Negative Supply Negative Supply Output half bridge 1A Output half bridge 1B Output half bridge 2A Output half bridge 2B Input of half bridge 1A Input of half bridge 1B Input of half bridge 2A Input of half bridge 2B 5V Regulator referred to ground 5V Regulator referred to +Vcc Stand-by pin (Control input) Hi-Z pin (Control input) Fault pin advisor (Open Collector Output) Configuration setting pin Thermal warning advisor (Open Collector Output) Logical ground High logical state setting voltage Not connected Ground for Vdd regulator Description
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FUNCTIONAL PIN STATUS
PIN NAME FAULT FAULT (*) TRI-STATE TRI-STATE PWRDN PWRDN THWAR THWAR(*) CONFIG CONFIG(**) Logical value 0 1 0 1 0 1 0 1 0 1 IC -STATUS Fault detected (Short circuit, or Thermal ..) Normal Operation All powers in Hi-Z state Normal operation Low absorpion Normal operation Temperature of the IC =130C Normal operation Normal Operation OUT1A=OUT1B ; OUT2A=OUT2B (IF IN1A = IN1B; IN2A = IN2B)
(*) : The pin is open collector. To have the high logic value, it needs to be pulled up by a resistor. (**:) To put CONFIG = 1 means connect Pin 24 (CONFIG) to Pins 21, 22 (Vdd)
PIN CONNECTION
GND-SUB OUT2B OUT2B VCC2B GND2B GND2A VCC2A OUT2A OUT2A OUT1B OUT1B VCC1B GND1B GND1A VCC1A OUT1A OUT1A N.C.
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18
D00AU1133
36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19
VCCSign VCCSign VSS VSS IN2B IN2A IN1B IN1A TH_WAR FAULT TRI-STATE PWRDN CONFIG IBIAS VDD VDD GND-Reg GND-Clean
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ABSOLUTE MAXIMUM RATINGS
Symbol VCE Vmax Top Tstg, Tj Parameter DC Supply Voltage (Pin 4,7,12,15) Maximum Voltage on pins (23 to 32) Operating Temperature Range Storage and Junction Temperature Value 40 5.5 0 to 70 -40 to 150 Unit V V C C
THERMAL DATA
Symbol Tj-case TjSD Twarn thSD Parameter Thermal Resistance Junction to Case (thermal pad) Thermal shut-down junction temperature Thermal warning temperature Thermal shut-down hysteresis 150 130 25 Min. Typ. Max. 2.5 Unit C/W C C C
ELECTRICAL CHARACTERISTCS (Ibias = 3.3V; Vcc = 28V; Tamb = 25C unless otherwise specified)
Symbol RdsON Idss gN gP Dt_s Dt_d td ON td OFF tr tf VCC VIN-H VIN-L IIN-H IIN-L VL VH Parameter Power Pchannel/Nchannel MOSFET RdsON Power Pchannel/Nchannel leakage Idss Power Pchannel RdsON Matching (*) Power Nchannel RdsON Matching (*) Low current Dead Time (static) Id=1A; Vcc=35V Id=1A Id=1A see test circuit no.1; see fig. 1 95 95 10 20 50 100 100 25 25 9 VOV Ibias/2 +300mV Ibias/2 -300mV Pin voltage=Ibias Pin voltage = 0.3V Ibias = 3.3V Ibias = 3.3V Ibias = 3.3V 0.8 1.7 1 1 35 Test conditions Min. Typ. 200 Max. 270 50 Unit m A % % ns ns ns ns ns ns V V V A A A V V
High current Dead Time (dinamic) L=22H; C = 470nF; Rl = 8 Id = 3.5A; see fig. 3 Turn-on delay time Turn-off delay time Rise time Fall time Supply voltage operating voltage High level input voltage Low level input voltage Hi level Input current Low level input current Low logical state voltage VL (pin PWRDN, TRISTATE) (note 1) High logical state voltage VH (pin PWRDN, TRISTATE) (note 1) Resistive load Resistive load Resistive load; as fig. 1 Resistive load; as fig. 1
IPWRDN-H Hi level PWRDN pin input current
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ELECTRICAL CHARACTERISTCS (continued) (Ibias = 3.3V; Vcc = 28V; Tamb = 25C unless otherwise specified)
Symbol IVCCPWRDN
Parameter Supply current from Vcc in Power Down Output Current pins FAULT -TH-WARN when FAULT CONDITIONS Supply current from Vcc in Tristate Supply current from Vcc in operation (both channel switching) Overcurrent Protection Threshold (short circuit current limit) (note 2) Overvoltage protection threshold Undervoltage protection threshold Output minimum pulse width
Test conditions PWRDN = 0
Min.
Typ.
Max. 3
Unit mA
IFAULT
Vpin = 3.3V Tri-state=0
1 22
mA mA
IVCC-hiz
IVCC
Input pulse width = 50% Duty; Switching Frequency = 384Khz; No LC filters; 3.5 30 No Load 70
80
mA
IOUT-SH VOV VUV tpw_min
6 35 7
8 40 150
A V V ns
Notes: 1. The following table explains the VL, VH variation with Ibias
Ibias 2.7 3.3 5
VLmin 0.7 0.8 0.85
VHmax 1.5 1.7 1.85
Unit V V V
Note 2: If used in single BTL configuration, the device may be not short circuit protected
LOGIC TRUTH TABLE (see fig. 2)
TRI-STATE 0 1 1 1 1 INxA X 0 0 1 1 INxB X 0 1 0 1 Q1 OFF OFF OFF ON ON Q2 OFF OFF ON OFF ON Q3 OFF ON ON OFF OFF Q4 OFF ON OFF ON OFF OUTPUT MODE Hi-Z DUMP NEGATIVE POSITIVE Not used
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Figure 1. Test Circuit.
OUTxY Vcc (3/4)Vcc Low current dead time = MAX(DTr,DTf) (1/2)Vcc (1/4)Vcc +Vcc t Duty cycle = 50%
M58
DTr OUTxY
M57
DTf
INxY
R 8
+ -
V67 = vdc = Vcc/2
D03AU1458
gnd
Figure 2.
+VCC
Q1 INxA OUTxA
Q2 OUTxB INxB
Q3
Q4
GND
D00AU1134
Figure 3.
High Current Dead time for Bridge application = ABS(DTout(A)-DTin(A))+ABS(DTOUT(B)-DTin(B)) +VCC Duty cycle=A Duty cycle=B
DTout(A) M58 Q1 OUTxA Rload=8 L67 22 C69 470nF DTout(B) L68 22 C70 470nF Q2 OUTxB M64
DTin(A) INxA
DTin(B) INxB
Iout=3.5A M57 Q3
Iout=3.5A Q4 M63
C71 470nF
Duty cycle A and B: Fixed to have DC output current of 3.5A in the direction shown in figure
D00AU1162
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Figure 4. Typical Quad Half Bridge Configuration
VCC1P IN1A IN1A +3.3V IBIAS CONFIG PWRDN R57 10K R59 10K C58 100nF TH_WAR IN1B VDD VDD VSS VSS C58 100nF C53 100nF C60 100nF IN2A VCCSIGN VCCSIGN IN2A GND-Reg GND-Clean 21 22 33 34 M17 35 8 9 36 31 20 19 M16 M15 OUTPR OUTPR 6 PGND2P R43 20 C43 330pF L13 22H C73 100nF R53 6 C83 100nF R66 5K REGULATORS 7 VCC2P PWRDN FAULT 23 24 25 27 26 TRI-STATE PROTECTIONS & LOGIC M5 28 30 M4 13 M2 29 M3 15 17 16 OUTPL OUTPL 14 PGND1P R41 20 C41 330pF L11 22H C71 100nF R51 6 C81 100nF R62 5K R61 5K
+VCC C21 2200F
C31 820F
C91 1F
12
VCC1N C51 1F OUTNL OUTNL PGND1N C61 100nF L12 22H R42 20 C42 330pF C72 100nF R52 6 C82 100nF R64 5K
11 10
TH_WAR IN1B
R63 5K
C32 820F
C92 1F
R65 5K
C33 820F
C93 1F
4
VCC2N C52 1F OUTNR OUTNR C62 100nF L14 22H R44 20 C44 330pF C74 100nF R54 6 C84 100nF R68 5K
3 2
IN2B
R67 5K
C34 820F
IN2B GNDSUB
32 M14
1
5
PGND2N
C94 1F
D03AU1474
Note: The diagran showed below, have been obtained using the demonstration board described in the application Note AN1456 (STA304 + STA500 Digital Audioprocessor evolution board evaluating manual - Jan 2002), refer to the schematic shown in fig. 1). For the Quad Half Bridge Configuration (fig. 4), refers to the application note AN1661 (STA308 Half Bridge Board - March 2003)
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Figure 5. Distortion vs Output Power (STA304A+STA500)
10
Figure 7. Output Power vs Supply Voltage (STA304A+STA500)
50
Pout (W)
45
5
2
Vcc=30V Rl=80hm f=1KHz
40
35
1
30
STA500 4 ohm load filter 22uH+ 0.47uF diff+ 0.1uF common mode
THD = 10%
0.5
25
% 0.2
20
THD = 1%
0.1
15
0.05
10
5
0.02
Eq.
0 +12 +12.5 +13 +13.5 +14 +14.5 +15 Vdc +15.5 +16 +16.5 +17 +17.5 +18
0.01 700m
1
2
3
4
5
6 W
7 8 9 10
20
30
40 50
Vsupply (V)
Figure 6. Tolal Power Dissipation & Efficiency vs Output Power
90 80
Pdiss
Figure 8. Output Power vs Supply Voltage (STA304A+STA500)
50
7 6 5 4
STA304A+STA500 1channel Vcc=25V Rl=8ohm F=1KHz
Pout (W)
45
40
70 Eff (%) 60 50 40 30 20 0 5 10 15 Pout (W) 20 25 30
Efficiency
Rload = 8 ohm f = 1KHz
THD = 10%
35
Pdiss (W)
30
3 2 1 0
25
THD = 1%
20
15
10
5 +12
+13
+14
+15
+16
+17
+18
+19
+20
+21
+22
+23
+24
+25
+26
+27 +28
Vcc (V)
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DIM. A a1 a2 a3 b c D (1) D1 E e e3 E1 (1) E2 E3 E4 G H h L N S
MIN. 0.10 0 0.22 0.23 15.80 9.40 13.90
mm TYP.
MAX. 3.60 0.30 3.30 0.10 0.38 0.32 16.00 9.80 14.50
MIN. 0.004 0 0.008 0.009 0.622 0.370 0.547
inch TYP.
MAX. 0.141 0.012 0.130 0.004 0.015 0.012 0.630 0.385 0.570
OUTLINE AND MECHANICAL DATA
0.65 11.05 10.90 5.80 2.90 0 15.50 0.80 11.10 0.429 2.90 6.20 0.228 3.20 0.114 0.10 0 15.90 0.610 1.10 1.10 0.031 10(max.) 8 (max.)
0.0256 0.435 0.437 0.114 0.244 0.126 0.004 0.626 0.043 0.043
PowerSO36
(1): "D" and "E1" do not include mold flash or protrusions - Mold flash or protrusions shall not exceed 0.15mm (0.006 inch) - Critical dimensions are "a3", "E" and "G".
N
N a2 A DETAIL A e3 H lead e A a1 E DETAIL A
c DETAIL B
D a3
36 19
slug BOTTOM VIEW E3
B E2 E1 DETAIL B
0.35 Gage Plane
D1
1
1
8
-C-
S h x 45 b
0.12
M
L
SEATING PLANE G C
AB
PSO36MEC
(COPLANARITY)
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Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics 2003 STMicroelectronics - All Rights Reserved
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(R)
DDX is a trademark of Apogee tecnology inc.

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